Hardware Architecture for Deep Learning

Introduction to the design and implementation of hardware architectures for efficient processing of deep learning algorithms and tensor algebra in AI systems. Topics include basics of deep learning, optimization principles for programmable platforms such as GPUs, design principles of custom accelerator architectures, co-optimization of algorithms and hardware, including sparsity, and architectural implications of precision reduction. Includes labs involving modeling and analysis of hardware architectures, architecting deep learning inference systems, and an open-ended final design project. Class adapted (with permission) from MIT class 6.5930 by Professors Joel Emer and Vivian Sze, including lectures and labs. For Seniors and Graduate level students.