Reconfigurable Computing

In this course, we will study computing platforms featured with CPUs + FPGAs (field-programmable gate arrays) for reconfigurable customized computing. We will first cover architecture and programming models for FPGAs as an accelerator platform using high-level synthesis (HLS). Various customization techniques on FPGAs, including customized control flow and data flow, accelerator memory management, performance & energy modeling and optimization, and communication & computation optimization, will be discussed. We will then cover various application domains that use FPGAs as accelerators, including deep learning, computer vision, natural language processing, security-related applications, etc. This course welcomes enrollment from both undergraduate (seniors) and graduate students (all).