Verification, Test, Synthesis

This course will provide an overview of algorithms and techniques in electronic design automation relating to the synthesis, verification, and test of digital integrated circuits. Some topics covered will include synthesis of two-level and multi-level circuits, logic minimization, representations of combinational and sequential circuits for design automation, ordered binary decision diagrams, equivalence checking, verification coverage, assertions, and automatic test pattern generation. Classic techniques and recent state-of-the-art research advances will both be discussed.