ELEC 5803
Behavioural Synthesis of ICs
Various topics related to computer analysis and synthesis of VLSI circuits including: logic synthesis, finite state machine synthesis, design methodologies, design for reuse, testing, common VLSI functions, a review of Verilog.
2025
Topics
- Overview of high-level synthesis and its significance
- Comparison with traditional design methodologies and current industry trends
- Behavioral Descriptions and Architectural Models
- Hardware description languages for behavioral synthesis
- Algorithmic-level hardware design
- Advanced target architectures
- High-Level Synthesis Tools
- Evolution of HLS and current industry trends
- Overview of modern tools and methodologies
- Open-Source Tools and Standards
- RISC-V based design and Industry standards and interoperability
- Emerging research directions
- Functional and Structural Verification
- Techniques for ensuring the correctness of synthesized designs
- Optimization Strategies
- Pipelining, parallelization, and other optimization techniques
- Trade-offs between hardware costs: performance, power, area, ...
- Advanced Algorithms and Methods
- ML-assisted synthesis
- HLS for multi-core and many-core systems
Readings
- Gajski, Daniel D., Nikil D. Dutt, Allen CH Wu, and Steve YL Lin. High—Level Synthesis: Introduction to Chip and System Design. Springer Science & Business Media, 2012.
- 6/6 Department of Electronics ELEC 5803 [0.5 credit] Faculty of Engineering, Carleton University, Behavioral Synthesis of ICs Ottawa, Canada. Winter 2025, Arash Ahmadi
Prerequisites & course information
Prerequisite(s): Some IC design knowledge such as given in ELEC 4708 .
Sources
- Course catalogue ↗2026–2027
- Behavioural Synthesis of ICs ↗2025