FORMAL VERIF HW SW SYSTEMS

3.00 points · University catalogue

Lect: 2. Introduction to the theory and practice of formal methods for the design and analysis of correct (i.e. bug-free) concurrent and embedded hardware/software systems. Topics include temporal logics; model checking; deadlock and liveness issues; fairness; satisfiability (SAT) checkers; binary decision diagrams (BDDs); abstraction techniques; introduction to commercial formal verification tools. Industrial state-of-art, case studies and experiences: software analysis (C/C /Java), hardware verification (RTL).