Computer Architecture and Hardware Acceleration

3 credits · Graduate

This course is a graduate-level seminar in computer architecture with special topics in hardware acceleration. This course surveys the landscape of hardware acceleration from historical contexts to recent trends in system designs spanning a collection of architectural techniques (e.g., stream processing, dataflow architecture, parallelism applied to acceleration) and a variety of application domains (e.g. GPU, ML, Database, Graph, Genomics). This course also covers the taxonomy of accelerators, the hardware-software co-design of accelerators, and the deployment of accelerators using the AWS cloud. Prerequisite: Computer Architecture (COMPSCI 250D/ECE 250 or COMPSCI 550/ECE 552) and Digital Logic Design (COMPSCI 350/ECE 350 or ECE 550) or consent of instructor.