6.004
Computation Structures
Spring 2017
Topics
- Unit 1: Basics of information: entropy, encodings, error correction
- Unit 2: The digital abstraction: combinational logic, voltage-based encoding
- Unit 3: CMOS: MOSFETs, gate design; timing
- Unit 4: Combinational logic: canonical forms, synthesis, simplification
- Unit 5: Sequential logic: latches, registers, timing
- Unit 6: Finite-state machines (FSMs); asynchronous inputs and metastability
- Unit 7: Performance measures: throughput and latency, pipelining
- Unit 8: Design tradeoffs: power, speed, area, throughput
- Unit 9: von Neumann architectures, Beta instruction set
- Unit 10: Assmbly language
- Unit 11: Compiling expressions and statements
- Unit 12: Stacks and procedures
- Unit 13: Beta implementation
- Unit 14: Multilevel memories: locality, performance, caches
- Unit 14: Cache design issues (continued)
- Unit 15: Pipelining the Beta: pipeline diagrams, data hazards
- Unit 15: Pipelining the Beta: control hazards, dealing with exceptions (continued)
- Unit 16: Virtual memory: mapping, protection, contexts
- Unit 17: Virtual machines: timesharing, OS kernels, supervisor calls
- Unit 18: Devices and interrupts; real-time
- Unit 19: Communicating processes: semaphores, synchronization, atomicity, deadlock
- Unit 20: System-level communication
- Unit 21: Parallel processing: performance limits, data- and thread-level parallelism
- Building a Better Beta: tips for the design project
Spring 2009
Topics
- Course overview and mechanics, basics of information
- Digital abstraction, combinational logic, voltage-based encoding
- CMOS technology, gate design, timing
- Canonical forms; synthesis, simplification
- Sequential logic
- Storage elements, finite state machines
- Synchronization, metastability
- Pipelining; throughput and latency
- Case study: multipliers
- Beta instruction set architecture, compilation
- Machine language programming issues
- Models of computation, programmable architectures
- Stacks and procedures
- Non-pipelined Beta implementation
- Multilevel memories; locality, performance, caches
- Cache design issues
- Virtual memory: mapping, protection, contexts
- Virtual machines: timesharing, OS kernels, supervisor calls
- Devices and interrupt handlers, preemptive interrupts, real-time issues
- Communication issues: busses, networks, protocols
- Communicating processes: semaphores, synchronization, atomicity, deadlock
- Pipelined Beta implementation, bypassing
- Pipeline issues: delay slots, annulment, exceptions
- Parallel processing, shared memory, cache coherence, consistency criteria
- Wrapup lecture
Sources
- Course catalogue ↗Historical OpenCourseWare
- MIT OpenCourseWare ↗Spring 2017
- MIT OCW calendar ↗
- MIT OCW syllabus ↗
- MIT OCW syllabus ↗
- MIT OCW calendar ↗
- Historical MIT OpenCourseWare offering. Named reading entries and schedule topics are automatically extracted from the linked source pages.
- Historical MIT OpenCourseWare offering. Named reading entries and schedule topics are automatically extracted from the linked source pages.