6.374
Analysis and Design of Digital Integrated Circuits
Fall 2003
Topics
- Challenges in Digital IC Design Course Overview
- CMOS Inverter I MOS Device Model with Sub-micron Effects VTC Parameters - DC Characteristics
- CMOS Inverter II CMOS Propagation Delay Parasitic Capacitance Estimation Layout of an Inverter Supply and Threshold Voltage Scaling SPICE Simulation Techniques
- Tutorial on Design Tools - Layout of a CMOS Gate, Extraction, SPICE, IRSIM
- CMOS Inverter III Components of Energy and Power Switching, Short-Circuit and Leakage Components SPICE Simulation Techniques
- Combinational Logic I Static CMOS Construction Ratioed Logic
- Combinational Logic II Pass Transistor / Transmission Gate Logic DCVSL Introduction to Dynamic Logic
- Combinational Logic III Dynamic Logic Design Considerations Power Dissipation in CMOS
- Combinational Logic IV Power Consumption in CMOS Logic (cont.) Leakage Power Dissipation Logical Effort Sizing - Performance Optimization of Digital Circuits
- Evening Session on Exploring Project Ideas Finish Arithmetic Structures and Project Ideas
- Guest Lecture by Prof. Tayo Akinwande Integrated CMOS Processing
- Sequential Circuits I Classification / Parameters Static Latches and Register
- Sequential Circuits II Race Condition Dynamic Latches and Registers Two Phase vs. Single Phase
- Sequential Circuits III Pulse Based Registers Latch vs. Register Systems Metastability
- Interconnect Capacitance Estimation Buffer Chains Low Swing Drivers Power Distribution
- Interconnect (cont.) Issues in Timing - Impact of Clock Skew and Jitter
- Clock Distribution Origins of Clock Skew / Jitter and Impact on Performance Clock Distribution Techniques Self-timed Circuits
- Memory I: ROM / EPROM / PLA Design Organization / Architecture Cell Design Sense-amplifiers PLA Folding Techniques Self-timing
- Memory II: SRAM Design Cell Design Differential Sense Amplifiers Self-timing
- Memory III DRAM Design Single Ended Sense Amplifier CMOS Scaling
- Advanced Voltage Scaling Techniques DC-DC Converter Design Performance Feedback Dynamic Voltage / Frequency Scaling
- Presentation of Final Projects
- Presentation of Final Projects (cont.)
Readings
- Project Schedule and Guidelines 11.1-11.6, 8
- LEC #: 11 · TOPICS: _Guest Lecture by Prof. Tayo Akinwande _ Integrated CMOS Processing · READINGS: 2
- Testing in VLSI
- Rabaey, Jan, Anantha Chandrakasan, and Bora Nikolic. Digital Integrated Circuits: A Design Perspective. 2nd ed. Prentice Hall, 2002.
- Material is also derived from the Journal of Solid-state Circuits and the International Solid-state Circuits Conference proceedings.
Sources
- Course catalogue ↗Historical OpenCourseWare
- MIT OCW readings ↗
- MIT OCW calendar ↗
- MIT OCW syllabus ↗
- Historical MIT OpenCourseWare offering. Named reading entries and schedule topics are automatically extracted from the linked source pages.