6.823
Computer System Architecture
Fall 2005
Topics
- History of Calculation and Computer Architecture (A)
- Influence of Technology and Software on Instruction Sets: Up to the Dawn of IBM 360 (A)
- Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A)
- Self-assessment Test and ISA
- Microprogramming (A)
- MIPS ISA, Bus-based Implementation, and Microprogramming
- Simple Instruction Pipelining (A)
- Pipeline Hazards (A)
- Microprogramming, Pipelining, and Hazards
- Multilevel Memories - Technology (J)
- Cache (Memory) Performance Optimization (J)
- ISAs, Microprogramming, Simple Pipelining and Hazards
- Virtual Memory Basics (J)
- Virtual Memory: Part Deux (A)
- Complex Pipelining (A)
- Caches, Virtual Memory
- Out of Order Execution and Register Renaming (A)
- Branch Prediction and Speculative Execution (A)
- Advanced Superscalar Architectures (J)
- Microprocessor Evolution: 4004 to Pentium 4 (J)
- Complex Pipelines
- Synchronization and Sequential Consistency (A)
- Cache Coherence (A)
- Cache Coherence (Implementation) (A)
- Snoopy Protocols (A)
- Sequential Consistency, Synchronization, Cache Coherence Protocols
- Relaxed Memory Models (A)
- SMPs, CC, Synch, Memory Models
- VLIW/EPIC: Statically Scheduled ILP (J)
- Vector Computers (J)
- Multithreaded Processors (J)
- Reliable Architectures (J)
- Vector Computers, Multithreading and Reliable Architectures
- Virtual Machines (J)
- VLIW/Vector/Threads
Readings
- H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture: A Quantitative Approach , 3rd ed. San Mateo, CA: Morgan Kaufman, 2002. ISBN: 1558605967.
- H&P2: Hennessy, J. L., and D. A. Patterson. Computer Architecture: A Quantitative Approach , 2nd ed. San Mateo, CA: Morgan Kaufman, 1995. ISBN: 1558603727.
- P&H: Patterson, D. A., and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface , 3rd ed. San Mateo, CA: Morgan Kaufman, 2004. ISBN: 1558606041.
- SES #: L1 · TOPICS: History of Calculation and Computer Architecture (A) · REQUIRED READINGS: H&P3, chapter 1, pp. 67-72.
- H&P2, chapter 1, pp. 53-60. Burks, Arthur W., Herman H. Goldstine, and John von Neumann. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument. Report to the U.S. Army Ordinance Department, 1946. Reprinted as: Bell and Newell. Computer Structures: Readings and Examples , chapter 4. New York, NY: McGraw-Hill, 1971. ISBN: 0070043574.
- Babbage, Charles, and Others. Charles Babbage and His Calculating Engines: Selected Writings. Edited by Philip and Emily Morrison . New York, NY: Dover, 1961. ISBN: 0486200124.
- SES #: L2 · TOPICS: Influence of Technology and Software on Instruction Sets: Up to the Dawn of IBM 360 (A) · REQUIRED READINGS: H&P3, rest of chapter 1.
- H&P2, rest of chapter 1. Amdahl, G. M., G. A. Blaauw, and F. P. Brooks, Jr. “Architecture of the IBM System/360.” IBM Journal of Research and Development , April 1964. Reprinted in: IBM Journal of Research and Development 44, no. 1/2 (2000).
- SES #: L3 · TOPICS: Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A) · REQUIRED READINGS: H&P3, chapter 2, pp. 90-129.
- H&P2, chapter 2, pp. 69-96.
- H&P3, chapter 2, pp. 129-158.
- H&P2, chapter 2, pp. 96-116.
- SES #: L5 · TOPICS: Simple Instruction Pipelining (A) · REQUIRED READINGS: H&P3, appendix A, pp. 2-11 (Background: P&H, chapter 6).
- H&P2, chapter 3, pp. 125-160 (Background: P&H, chapter 6).
- SES #: L6 · TOPICS: Pipeline Hazards (A) · REQUIRED READINGS: H&P3, appendix A, pp. 11-37.
- H&P2, chapter 3, pp. 161-178.
- SES #: L7 · TOPICS: Multilevel Memories - Technology (J) · REQUIRED READINGS: H&P3, chapter 5, pp. 390-413.
- H&P2, chapter 5, pp. 373-390.
- SES #: L8 · TOPICS: Cache (Memory) Performance Optimization (J) · REQUIRED READINGS: H&P3, chapter 5, pp. 413-460 and 478-489.
- H&P2, chapter 5, pp. 390-439 and 457-474. Jouppi, Norm. “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers.” In The Proceedings of 17th International Symposium on Computer Architecture (ISCA) Seattle, Washington, May 1990, pp. 364-373.
- H&P3, chapter 5, pp. 460-478.
- H&P2, chapter 5, pp. 439-457.
- SES #: L10 · TOPICS: Virtual Memory: Part Deux (A) · REQUIRED READINGS: H&P3, appendix A, pp. 37-47.
- H&P2, chapter 3, pp. 187-214.
- SES #: L11 · TOPICS: Complex Pipelining (A) · REQUIRED READINGS: H&P3, appendix A, pp. 37-78.
- SES #: L12 · TOPICS: Out of Order Execution and Register Renaming (A) · REQUIRED READINGS: H&P3, chapter 3, pp. 172-196.
- H&P2, chapter 4, pp. 221-261.
- H&P3, chapter 3, pp. 196-259.
- H&P2, chapter 4, pp. 262-289 and 317-335.
- SES #: L15 · TOPICS: Microprocessor Evolution: 4004 to Pentium 4 (J) · REQUIRED READINGS: H&P3, chapter 3, pp. 259-283.
- H&P2, chapter 4, pp. 335-359.
- SES #: L16 · TOPICS: Synchronization and Sequential Consistency (A) · REQUIRED READINGS: H&P3, chapter 6, pp. 549.
- H&P2, chapter 8, pp. 694-713.
- SES #: L17 · TOPICS: Cache Coherence (A) · REQUIRED READINGS: H&P3, chapter 6, pp. 549-590.
- H&P2, chapter 8, pp. 654-693.
- SES #: L18 · TOPICS: Cache Coherence (Implementation) (A) · REQUIRED READINGS: H&P3, chapter 6, pp. 549-590.
- SES #: L20 · TOPICS: Relaxed Memory Models (A) · REQUIRED READINGS: H&P3, chapter 6, pp. 607-608 and 618-619.
- H&P2, chapter 8, pp. 714-720. Adve, S., and K. Gharachorloo. “Shared memory consistency models: a tutorial.” In Technical Report WRL-TR 95/7, Digital Western Research Laboratory, September 1995.
- SES #: L21 · TOPICS: VLIW/EPIC: statically Scheduled ILP (J) · REQUIRED READINGS: H&P3, chapter 4, pp. 304-362.
- H&P2, Chapter 4, pp. 223-240 and 284-317.
- SES #: L22 · TOPICS: Vector Computers (J) · REQUIRED READINGS: H&P3, appendix G.
- SES #: L23 · TOPICS: Multithreaded Processors (J) · REQUIRED READINGS: H&P3, chapter 3, pp.272-273.
- H&P3, chapter 6, pp. 608-615 and 635-636. Tullsen, D., S. Eggers, and H. Levy. “Simultaneous Multithreading: Maximizing On-Chip Parallelism.” In The Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995.
- Tullsen, D., S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.” In The Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996.
- Reinhardt, S. K., and S. S. Mukherjee. “Transient Fault Detection via Simultaneous Multithreading.” In The Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.
- Biswas, R., R. Cheveresan, J. Emer, S. Mukherjee, P. Racunas, and R. Rangan. “Computing Architectural Vulnerability Factors for Address-Based Structures.” In The Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.
- SES #: L25 · TOPICS: Virtual Machines (J) · REQUIRED READINGS: H&P3, pp. 367-370.
- Hennessy, J. L., and D. A. Patterson. Computer Architecture: A Quantitative Approach , 3rd ed. San Mateo, CA: Morgan Kaufman, 2002. ISBN: 1558605967.
- This is the main textbook used in this course. We also give the equivalent readings for the 2nd edition of this book to allow you to use a secondhand copy. In previous years, some students found that the lecture notes were sufficient to learn the material and that the textbook was unnecessary, but we nevertheless recommend the book as a good reference guide.
- Patterson, D. A., and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface , 3rd ed. San Mateo, CA: Morgan Kaufman, 2004. ISBN: 1558606041.
Sources
- Course catalogue ↗Historical OpenCourseWare
- MIT OCW calendar ↗
- MIT OCW readings ↗
- MIT OCW syllabus ↗
- Historical MIT OpenCourseWare offering. Named reading entries and schedule topics are automatically extracted from the linked source pages.