System Design and Testing using JTAG Boundary Scan

3 credits

Introduction to JTAG boundary scan: IEEE 1149.x Standard; design for boundary-scan testability(DFT); connection and functional testing using on-board JTAG devices such as CPU, CPLD, FPGA; testing of non-JTAG devices such as passive devices, logic devices and memory; debugging using boundary-scan. Other test methods are also covered.