Physical Design Automation for VLSI and FPGAs

Graduate

Introduction to backend CAD flow for VLSI and FPGAs; algorithms and CAD tools for technology mapping, floor planning, partitioning, placement and routing; exposure to timing analysis and timing-driven layout; assignments will involve use of academic and/or industrial CAD tools as well as development of simple CAD tools for specific layout tasks. (3 lecture hours a week.) (Prerequisites: consent of the instructor.)