DIGITAL SYSTEM DESIGN AND SYNTHESIS
Introduction to the use of hardware description languages and automated synthesis in design. Advanced design principles. Verilog and VHDL description languages. Synthesis from hardware description languages. Timing-oriented synthesis. Relation of integrated circuit layout to timing-oriented design. Design for reuse.
Prerequisites & course information
Requisites: E C E/COMP SCI 352 , graduate/professional standing, or member of Engineering Guest Students Repeatable for Credit: No Last Taught: Fall 2026 Learning Outcomes: 1. Describe a digital design using a Hardware Description Language (HDL) such that it will synthesize efficiently using the intended mix of sequential and combinational cells. Demonstrate proficiency in coding in both dataflow and behavioral HDL styles Audience: Undergraduate 2. Write a thorough testbench to validate a digital design. This includes consideration of corner test cases and ensuring testbench is self-checking Audience: Undergraduate 3. Simulate and debug a digital design using a HDL simulator Audience: Undergraduate 4. Constrain and Synthesize a digital design targeting a standard cell library. Explore options and methods to optimize synthesis results for speed/power/area. Interpret static timing reports generated by synthesis tool Audience: Undergraduate 5. Partition and complete the implementation (design/validation/synthesis) of a complex digital system as a member of a project team Audience: Undergraduate Learning Outcomes: 1. Describe a digital design using a Hardware Description Language (HDL) such that it will synthesize efficiently using the intended mix of sequential and combinational cells. Demonstrate proficiency in coding in both dataflow and behavioral HDL styles Audience: Undergraduate 2. Write a thorough testbench to validate a digital design. This includes consideration of corner test cases and ensuring testbench is self-checking Audience: Undergraduate 3. Simulate and debug a digital design using a HDL simulator Audience: Undergraduate 4. Constrain and Synthesize a digital design targeting a standard cell library. Explore options and methods to optimize synthesis results for speed/power/area. Interpret static timing reports generated by synthesis tool Audience: Undergraduate 5. Partition and complete the implementation (design/validation/synthesis) of a complex digital system as a member of a project team Audience: Undergraduate
Sources
- Course catalogue ↗2026-2027