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E C E 553

TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS

3 credits.

Faults and fault modeling, test equipment, test generation for combinational and sequential circuits, fault simulation, memory and microprocessor testing, design for testability, built-in self-test techniques, and fault location.

Prerequisites & course information

Requisites: COMP SCI/E C E 352 and COMP SCI 300 , graduate/professional standing, or member of Engineering Guest Students Course Designation: Grad 50% - Counts toward 50% graduate coursework requirement Repeatable for Credit: No Last Taught: Fall 2026 Learning Outcomes: 1. Identify factors that impact economics of testing of integrated circuits Audience: Both Grad & Undergrad 2. Model and simulate faults that can occur in integrated circuits Audience: Both Grad & Undergrad 3. Apply state-of-the-art test generation algorithms Audience: Both Grad & Undergrad 4. Utilize design for testability and built-in self-test techniques Audience: Both Grad & Undergrad 5. Generate tests to detect path delay faults Audience: Graduate Learning Outcomes: 1. Identify factors that impact economics of testing of integrated circuits Audience: Both Grad & Undergrad 2. Model and simulate faults that can occur in integrated circuits Audience: Both Grad & Undergrad 3. Apply state-of-the-art test generation algorithms Audience: Both Grad & Undergrad 4. Utilize design for testability and built-in self-test techniques Audience: Both Grad & Undergrad 5. Generate tests to detect path delay faults Audience: Graduate

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